Although Ethernet is known as a networking and system-to-system protocol, it has been adapted to other applications, including the backplane. Ethernet is a popular protocol choice in FPGAs because of its flexibility, reliability, and performance.
Whether you are designing low cost 10/100 Mbps Ethernet applications with Spartan™ 6 FPGAs or 400G Ethernet applications with Virtex™ UltraScale+™ or Versal™ FPGAs, AMD has an Ethernet solution for you.
Implemented in 7-nm technology, the Versal ACAP device incorporates an integrated dynamically switchable 10G, 25G, 40G, 50G and 100G multrate Ethernet Subsystem (MRMAC) and a 100G, 200G, and 400G channelized multirate Ethernet Subsystem (DCMAC). These two IP blocks also support IEEE and consortium FECs for PAM-4 and NRZ applications as well 1588 hardware timestamping. In additional, these blocks allow for configurations such as FEC only, PCS only, and MAC only modes.